1. Field of Invention
This invention relates to a method for automatically setting voltage levels among otherwise interchangeable CPUs, and, more particularly, to a method for determining whether a CPU is a single-voltage device having a unified voltage plane or dual-voltage device having split voltage planes, for determining which voltage(s) are to be applied to the CPU, and for applying appropriate voltage(s) to the CPU voltage plane(s).
2. Description of the Related Art
There are many central processing units (CPUs) which can be used interchangeability within computing systems. This interchangeability promotes an ability to use multiple CPU sources in the manufacture of similar computing systems and to replace one type of CPU with another, in order to repair a computing system having a failing CPU or in order to upgrade the computing system with features available with a new CPU.
A serious obstacle to many types of CPU interchangeability lies in the different voltage requirements of various CPUs. For example, many conventional types of Intel PENTIUM processors, such as model #P54 CTA, use a unified voltage plane (UVP), with the same supply voltage being applied to all voltage pins of the CPU, while the Intel PENTIUM MMX processors, such as model #P55C, use a split voltage plane (SVP), so that a core voltage can be applied to certain pins of the processor while an I/O voltage is applied to other pins of the processor. CPUs from other manufacturers follow a similar pattern, with UVP types requiring a single voltage, and with SVP types requiring two different voltages. In addition to configurational variations in the number of voltage levels required, the individual voltage level requirements vary from one CPU manufacturer to another and among the various models of a single manufacturer. A single pin, generally labeled VCC2DET, is provided in various similar types of processors to aid in the determination of the core voltage of the CPU. This pin is either grounded or floating. Certain CPUs from AMD also provide a second pin for voltage identification. However, these pins are inadequate for distinguishing among the different configurations and voltage levels. Thus, what is needed is a method for distinguishing between UVP-type and SVP-type CPUs and for determining the voltage(s) which should be applied to a particular installed CPU.
A conventional voltage regulation circuit for supplying voltage to a CPU has a DC to DC converter, a feedback resistor and a fixed resistor. The output voltage of the DC to DC converter is returned to the input of this converter through the feedback resistor, and the fixed resistor is tied between the input of the converter and electrical ground. The values of the feedback resistor and the fixed resistor determine the output voltage of the DC to DC converter. This circuit is made variable, so that several voltages needed by various CPUs can be alternately produced, by replacing the feedback resistor with several resistors wired in a parallel circuit, with these resistors being individually selectable through the use of DIP switches or jumpers. The difficulties associated with setting the DIP switches or jumpers properly, together with the possible occurrence of defective contact surfaces due to oxidation, are disadvantages of this method.
U.S. Pat. No. 5,867,715 describes an apparatus for programmably converting the operating voltage of the CPU and chipset by means of the firmware programmably setting the operating voltage, instead of by means of adjusting jumpers. The apparatus includes an address decoder unit, a programmable data memory, a DC to DC converter and a feedback resistance switching circuit. In operation, the CPU and chipset output an address signal and digital data which is decoded by an address decoder unit. After identifying the address data, the address decoder unit generates a trigger signal and writes input data specifying the operating voltage to a programmable data memory, which is a non-volatile device, such as a FLASH EEPROM or an EEPROM programmed through the use of a programmable burner operating in response to the data from the address decoder unit. Output signals from the programmable data memory drive inputs to a feedback resistance switching circuit, so that the resistance of the feedback path of the DC to DC converter is varied according to data stored in the programmable data memory. Since the programmable data memory is nonvolatile, the data is not lost when the computing system is turned off and on. However, if the CPU is to be replaced, it must be replaced with the system turned off. If this occurs, and if the replacement CPU has different voltage requirements than the CPU which has been replaced, this apparatus does not provide an automatic means for changing the operating voltage. Thus, what is needed is a system which determines the operating voltage in an automatic fashion as the computing system is turned on.
U.S. Pat. No. 5,632,039 describes a circuit that automatically switches the power supply voltage PVDD provided to a CPU between 3.3 volts and 5 volts. The circuit detects whether the CPU installed in a socket is a 3.3-volt part or a 5-volt part by determining the state of a voltage detect sense pin provided by the socket. If the voltage detect sense pin is driven low, that indicates a 3.3-volt CPU is being used. If a 5-volt CPU is installed, the voltage detect sense pin is left floating by the CPU, which allows a pullup resistor to pull the voltage detect sense pin high. The power supply voltage provided to the CPU is regulated through a power field effect transistor (FET). The gate of the power FET is connected to the output of a voltage reference source and is coupled to a 12-volt supply signal. If the voltage detect sense pin is pulled high, the voltage reference source is turned off, allowing the 12-volt signal to drive the gate of the power FET. This in turn allows the power FET to pass a 5-volt supply signal to the CPU supply signal PVDD. If the voltage detect sense pin is pulled low, the voltage reference source is turned on to drive the gate of the power FET to approximately one threshold voltage above 3.3 volts. In response, the power FET passes only 3.3 volts to the CPU supply signal PVDD.
One method for providing for the use of both UVP and SVP processor types on a single mother board requires a physical connection or disconnection between the core and I/O voltage planes within the motherboard. For a UVP processor, these voltage planes are tied together by jumpers or low resistance resistors. For an SVP processor, these jumpers or resistors are removed, with these voltage planes being connected to separate power supplies. If they are soldered in placed, they must be unsoldered. This requirement for proper identification of the processor type and for physical manipulation of the motherboard creates a risk of processor damage if the jumpers are incorrectly installed for the processor being used. What is needed is a method for automatically identifying whether the processor is UVP or SVP type and for making the appropriate electrical connections without requiring operator intervention.
A second method for providing for the use of both UVP and SVP processor types on a single mother board requires the mother board to be configured with split voltage planes, which are not connected to one another. To convert the mother board for use with a UVP processor, the respective voltage planes of the mother board are coupled inside the processor package. A single voltage is supplied to the core voltage plane of the mother board, and the I/O voltage plane of the mother board is then supplied with voltage through the lead frame. Since electrical power for the I/O voltage plane within the UVP processor, and possibly for other devices on the motherboard, must be fed through the lead frame of the processor system requirements may easily exceed the specifications of the processor. What is needed is a method for automatically switching the I/O voltage plane without causing current for the I/O voltage plane to be drawn through the lead frame.
U.S. Pat. No. 5,737,171 describes a embodiment providing a voltage comparator that senses whether a processor coupled to a mother board is a unified or split voltage plane type. Initially, when power is applied to the mother board 1, the voltage regulators are set with a core regulator supplying a correct core voltage, such as 3.3 volts, to pins which would be connected to the core voltage plane of a split voltage plane processor, and with an I/O regulator supplying its lowest voltage, such as 1.25 volts, to pins which would be connected to the I/O voltage plane of a split voltage plane processor. If the processor is a UVP type, the core voltage, less a voltage drop due to resistance within the processor package is driven into the I/O voltage plane, causing the I/O regulator, operating at a much lower voltage, to shut down. If the processor is an SVP type, the I/O voltage remains at 1.25 volts. After the POWERGOOD signal from the power supply reaches a logic high level, indicating that the system voltages are at valid states, latches are set to hold a multiplexer providing inputs to a voltage regulator at the necessary levels. The voltage level of the VCC2DET pin is also used to:vary the output voltage of the core regulator by switching a P-channel FET to change the voltage applied to an input pin of the regulator.
Intel PENTIUM Pro processors operate optimally at a voltage supply level specified by the manufacturer for each individual unit. U.S. Pat. No. 5,774,736 describes a fault-tolerant system having two such processors, each of which is powered by the output of a DC-DC converter. Each DC-DC converter provides a voltage in accordance with a four-bit voltage selection code VIDA less than 3..0 greater than  provided, in a first embodiment, through the settings of DIP switches, or, in a second embodiment, through programming provided by the CPU. While this system provides for voltage adjustments to accommodate a particular type of CPU requiring such adjustments for individual devices, what is needed is voltage adjusting circuitry usable with a number of different types of CPUs, and, particularly with CPUs having both single and dual voltage requirements.
Modern but conventional processors include means for providing an identifier, often called a CPUID, in response to a query for such information by the software of a computer system. An example of apparatus for providing such information is found in U.S. Pat. No. 5,671,435, which describes the use of a specialized set of read-only identification (ID) registers to store information relating to a microprocessor and its associated attributes, so that microcode is not needed to sequence through steps to obtain such processor identification. When the processor is manufactured, corresponding processor information is programmed into the ID registers. Later, when the processor is being used, software can generate a simple instruction to access registers to retrieve information that identifies the processor and its attributes. The software can access a base ID (or identifier) register which includes family (type) model, and step ID for the processor, as well as the number of xe2x80x9cnamexe2x80x9d and xe2x80x9cfeaturexe2x80x9d registers present for conveying additional information pertaining to these attributes.
Another example of apparatus for providing processor identifying information is found in U.S. Pat. No. 5,794,066, which describes a multi-level identification apparatus and method for providing at least two types of identifying information, including a first type for identifying the origin of the microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of the microprocessor. The apparatus includes first and second memory elements and control logic for executing an ID instruction, storing data in one or more general registers for selective reading by a program. This method is available at any time while the microprocessor is running.
What is needed is a method for using the processor identifying information stored within the processor to determine the exact operating core voltage for the processor, so that it will be operated according to the correct specifications.
In accordance with a first aspect of the present invention, apparatus is provided for providing electrical power within a computing system, with the apparatus including a programmable power supply, instruction storage, decode logic, first and second data connections, and a first electrical power supply line. The programmable power supply produces a variable output voltage as a function of a program input code. The instruction storage, which is accessed by the processor during each power initialization sequence, holds a program for execution within the processor. This program includes an instruction causing the processor to provide a processor identifying code indicating a type of the processor. The processor identifying code is transmitted over the first data connection, between the processor and the decode logic. The program input code is transmitted over the second data connection, between the decode logic and the programmable power supply. Electrical current is driven along the first electrical power supply line between the programmable power supply and a first power input to the processor. The programmable power supply is preferably implemented as a DC to DC convertor having a number of input pins to which the program input code is applied. The decode logic preferably includes a register storing data, determined from the processor identifying code, so that the program input code is continuously generated.
The first power input to the processor is preferably those processor pins which are connected to the core voltage plane of a split-voltage plane type of processor, while the second power input to the processor is preferably those processor pins which are connected to the I/O voltage plane of a split-voltage plane type of processor. Since, when a new processor is installed, it is undetermined whether it is a unified- or split-voltage plane type, these are treated as separate voltage inputs, even through they may be electrically connected within the processor chip in a unified-voltage-plane processor.
In accordance with a second aspect of the present invention, apparatus is provided for providing electrical power having first and second power inputs within a computing system, with the apparatus including a first power supply connected to the first power input of the processor, a second power supply and a switching circuit. The switching circuit determines if the processor is a unified voltage plane type or a split voltage plane type, and connects the first power supply to the second power input of the processor if the processor is of the unified voltage plane type and connects the second power supply to the second power input of the processor if the processor is of the split voltage plane type.
In accordance with a third aspect of the present invention, a determination is first made, after power-on, of whether a processor is of a unified voltage plane type or a split voltage plane type. If the processor is of the unified voltage plane type, a first voltage level is applied to first and second power inputs of the processor. If the processor is of the split voltage plane type, the first voltage is applied to the second power input of the processor, and a second voltage is applied to the first power input of the processor. The processor then begins running an initialization program. An instruction within the initialization program causes the processor to transmit a processor identifying code to decode logic, which causes a third voltage to be applied to the first power input of the processor, with the third voltage being determined as a function of the processor identifying code. Preferably, the processor is determined to be a unified voltage plane if a first pin of the processor is determined to be electrically floating and to be a split voltage plane type if the first pin is determined to be electrically grounded. Preferably, the second voltage is determined in accordance with whether a second pin of the processor is absent or present and electrically grounded.